library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sync_rom is
generic (data_length : natural := 16;
add_length : natural := 10);
port ( clk : in std_logic;
address : in std_logic_vector(add_length-1 downto 0);
data_out : out std_logic_vector(data_length-1 downto 0)
);
end sync_rom;
architecture synth of sync_rom is constant mem_size : natural := 2**add_length;
type mem_type is array (mem_size-1 downto 0) of
std_logic_vector (data_length-1 downto 0);
constant mem : mem_type := (0 => x"abcd", 1 => x"beef",
2 => x"5555", 3 => x"1010",
4 => x"5a6b", 5 => x"f0f0",
6 => x"1234", 7 => x"fabc",
8 => x"2345", 9 => x"9876",
10 => x"5432", 11 => x"6666",
12 => x"0101", 13 => x"abab",
others => x"4247");
begin
rom : process (clk)
begin
if rising_edge(clk) then
data_out <= mem(to_integer(unsigned(address)));
end if;
end process rom ;
end architecture synth;