DDSPipelined (DDS.v)

Simplified block diagram

This module is a signal generator that outputs I/Q vectors with a given phase increment between samples. It is phase continuous with respect to changes of frequency and, once started, runs until it is reset. Performance information is available in the documentation of the Cordic module. This module is the pipelined version of the serial DDS module.

Ports

clkinputThe clock input.
resetinputThe reset input. Use this port to stop the DDS and output zero.
goinputA multi-bit trigger to start conversions.
gonowoutputPulsed when all trigger conditions have been met. It is this pulse that starts the DDS.
PhIncrinputThe phase increment per clock on a 2wpa phase scale per revolution.
I, QoutputThe I/Q-pair output.
busyoutputWhen asserted, The DDS is running and outputting I/Q pairs.

Parameters

Parameters, their defaults, and descriptions:

wd16The bit width of the outputs I, Q, IN, QN, and out.
apb0Extra internal bits of precision of the Cordic computation.
wpawd+apb+1The width of the internal phase accumulator and phase-increment port. A phase of 2wpa corresponds to 360 degrees. The port PhIncr is added to the accumulator every clock cycle.
gb1The width of the go trigger vector.

Notes

Example instantiation:

// data and phase bit widths
localparam	wd = 16, wpa = wd+1;

// start trigger input; can have multiple bits
wire				go;

// stop trigger input
wire				stop;

// dds outputs
wire	signed	[wd-1:0]	I, Q;	// I/Q vector
wire				busy;	// asserted when DDS is running

// frequency = 28.2 MHz (= -11.8 MHz) @ clk = 40 MHz
wire		[wpa-1:0]	freq = 92389;

DDSPipelined 
    #(.wd(wd), .wpa(wpa))
    instancename (
        .clk(clk),		.reset(stop),
        .go(go),		.PhIncr(freq),
        .I(I),			.Q(Q),
        .busy(busy)
    );