This module is a signal generator that outputs I/Q vectors with a given phase increment between samples. It is phase continuous with respect to changes of frequency and, once started, runs until it is reset. Performance information is available in the documentation of the Cordic module. This module is the pipelined version of the serial DDS module.
clk | input | The clock input. |
reset | input | The reset input. Use this port to stop the DDS and output zero. |
go | input | A multi-bit trigger to start conversions. |
gonow | output | Pulsed when all trigger conditions have been met. It is this pulse that starts the DDS. |
PhIncr | input | The phase increment per clock on a 2wpa phase scale per revolution. |
I, Q | output | The I/Q-pair output. |
busy | output | When asserted, The DDS is running and outputting I/Q pairs. |
Parameters, their defaults, and descriptions:
wd | 16 | The bit width of the outputs I, Q, IN, QN, and out. |
apb | 0 | Extra internal bits of precision of the Cordic computation. |
wpa | wd+apb+1 | The width of the internal phase accumulator and phase-increment port. A phase of 2wpa corresponds to 360 degrees. The port PhIncr is added to the accumulator every clock cycle. |
gb | 1 | The width of the go trigger vector. |
f = fs × PhIncr/2wpawhere fs is the data (clock) rate. An updated I/Q pair is available at the I and Q output ports each clock. The delay between the PhIncr port and the I and Q ports is wd-1 clocks.
// data and phase bit widths localparam wd = 16, wpa = wd+1; // start trigger input; can have multiple bits wire go; // stop trigger input wire stop; // dds outputs wire signed [wd-1:0] I, Q; // I/Q vector wire busy; // asserted when DDS is running // frequency = 28.2 MHz (= -11.8 MHz) @ clk = 40 MHz wire [wpa-1:0] freq = 92389; DDSPipelined #(.wd(wd), .wpa(wpa)) instancename ( .clk(clk), .reset(stop), .go(go), .PhIncr(freq), .I(I), .Q(Q), .busy(busy) );