Debounce.v

This module synchronizes transition to a clock by generating a single-period pulse in response to an incoming pulse of arbitrary duration. No further pulses are generated until the input goes low. The figure shows the state diagram.

Ports | Parameters | Notes | Example

Ports

clk	input	The clock input.
in	input	The pulse input from which to generate the output pulse.
out	output	The output-pulse port. It is the same as `state == pulse;`

Parameters

There are no configurable parameters.

Notes

This module could alternatively be coded in terms of the Trigger module and included in Trigger.v, and the file Debounce.v retired.

Example instantiation in Verilog:

Debounce db (.clk(clk), .in(in), .out(out));

10/3/2014