Verilog modules: FourierIQ.v

FourierIQ.v

This module Fourier analyzes one or more I/Q data streams into four Fourier integrals that integrate for as long as it is enabled. The number of signals analyzed is selected by a parameter. Two DDS inputs in I/Q data streams (I, Q, -I, -Q, ...), one shifted 90 degrees with respect to the other, are required.

Ports

clk input The clock input.

reset input The reset input.

en input Enables accumulate/shift operations on that clock cycle. enacc must also be asserted for accumulate to occur. It should be asserted for a multiple of four clock cycles per integration cycle.

enacc input Enables accumulate on that clock cycle. It has no effect if en is not asserted. It is asserted for two consecutive clocks per accumulate with interval that can range down to zero.

in1, in1_90 input The dds inputs. The latter is shifted 90 degrees with respect to the former.

in2 input The one signal input in an I/Q data stream.

out output The four integral concatenated into a single vector.

Parameters

Parameters, their defaults, and descriptions:

wi1	11	The bit width of the first two (dds) inputs ports.
wi2	16	The bit width of third (signal) input port.
wo	13	The bit width of the output port.
ofl	6	The number of accumulator overflow bits.
apb	3	The number of accumulator precision bits. These least-significant bits are used during accumulation but discarded from the output as a means to control accumulated quantization error.

Example instantiation:

localparam
	wdds = 16,	wd  = 15, 	wo = 13,
	ofl  = 15,	apb = 11;

wire		[4*wo-1:0]	fourier;
wire		[wd-1:0]	signal;
wire		[wdds-1:0]	ddsout, ddsout90;

FourierIQ
    #(.wi1(wdds), .wi2(wd), .wo(wo), .ofl(ofl), .apb(apb))
    FourierAnalyser (
        .clk(clk),		.reset(reset),
        .en(en),		.enacc(ddst1 || ddst2),
        .in1(ddsout),		.in1_90(ddsout90),
        .in2(signal),
        .out(fourier)
    );

clk	input	The clock input.
reset	input	The reset input.
en	input	Enables accumulate/shift operations on that clock cycle. `enacc` must also be asserted for accumulate to occur. It should be asserted for a multiple of four clock cycles per integration cycle.
enacc	input	Enables accumulate on that clock cycle. It has no effect if `en` is not asserted. It is asserted for two consecutive clocks per accumulate with interval that can range down to zero.
in1, in1_90	input	The dds inputs. The latter is shifted 90 degrees with respect to the former.
in2	input	The one signal input in an I/Q data stream.
out	output	The four integral concatenated into a single vector.