IQDetector.v
This module implements I/Q detection via offset-binary converson and a 1-z-2 filter of a data stream as implemented in Hengjie's code.
Ports
| clk | input | The clock input. |
| reset | input | The reset input. |
| din | output | Input data stream. |
| dout | output | Output data stream |
Parameters
| wid | 14 | Width of the input data stream. |
Notes
- The output is one bit wider than the input.
- The arithmetic is signed.
Example instantiation in Verilog:
wire [11:0] d1;
wire [12:0] d2;
IQDetector #(.wid(12)) iq0(.clk(clk), .reset(reset), .din(d1), .dout(d2));