InterpIncr.v

First a summary about the interpolation scheme for which this module is intended. Ramp waypoints are available periodically, and the slope of the ramp is approximated by the step from one waypoint to the next divided by the interval between waypoints. In this interpolation scheme, the ramp between two waypoints is incremented in the correct direction (up or down) every n clock cycles, where n is the integer nearest the reciprocal of the slope. This module module takes the interval between waypoints and the increment from one waypoint to the next, computes the reciprocal slope n, generates internal pulses that are interpreted as the times at which to increment the ramp and the direction (up or down), and accumulates the increments, which is returned and added to the first of the two waypoints in the enclosing module. When the next waypoint increment is available, the increment is reset and the cycle is repeated. This module is instantiated twice, once each for the interleaved I and Q components.

Ports

clk	input	The clock input.
reset	input	The reset input.
en	input	An enable input. The state of the module is frozen when at logic zero.
go	input	Command to initiate a cycle.
interval	input	The interval in clocks between waypoints.
step	output	The difference between successive waypoints.
incr	output	The accumulated increments.

Parameters

dwidth		Width of the signed step input, chosen large enough to handle the largest anticipated step.
iwidth		Width of the inter-waypoint interval input, chosen to accommodate the largest expected interval. For example, if the clock is 40 MHz, the longest ramp is 10 s, and there are 512 waypoints in that ramp, then `iwidth` must be at least 20.
swidth		Width of the word holding the accumulated ramp increment between waypoints (default `dwidth`; it should not need to be changed).
xwidth		Width of the internal word holding the timer interval between increments (reciprocal slope n; default 8).

Notes

If the increment interval is off scale, it is very long and no increments are applied to the ramp.
The increment timer restarts itself after it completes each cycle. To discontinue, assert the reset port. Otherwise it continues indefinitely. There is no done signal because the module ordinarily does not terminate.
This module can only handle slowly changing ramps. It cannot interpolate at large frequency offsets, such as at a coupled-bunch mode line.
Rounding of the result of the division is employed, which improves the accuracy of the calculated increment interval.

Example instantiation in Verilog:

wire		[14:0]	step;
wire		[19:0]	interval;
wire		[ 7:0]	incr;

InterpIncr
    #(.dwidth(15), .iwidth(20), .swidth(10), .xwidth(8))
    InterpIncr_inst (
        .clk(clk), 
        .reset(reset),
        .en(en),
        .go(go), 
        .interval(20000),
        .step(step),
        .incr(incr),
        .busy(busy)
    );