QuadrantLatch.v

This module latches the I and Q parts of an interleaved I/Q data stream given a quadrant fiducial, optionally averaging the samples. The diagram shows the basic structure without averaging.

Simplified block diagram

Ports

clkinputThe clock input.
ininputThe I/Q signal to be sampled.
quadinputThe quadrant fiducial. The I part is sampled when quad = 002 and Q when quad = 012.
outoutput    A double-width output consisting of the sampled I and Q parts.

Parameters

w1Width of the input port (default 16).
w2Width of the output port (default w1).