RampInterp.v

This module provides a ram buffer in which to hold a ramp waypoint table for both I and Q components of a waveform. The buffer is filled by a host via a host interface. When triggered, the module then clocks out the waypoints at a rate also determined by the host, and interpolates between them so as to provide a smoothly changing ramp.

Ports | Parameters | Notes | Example | Illustration

Ramp ports

clkinputThe clock input.
resetinputThe reset input.
eninputAn enable input. The state of the module is frozen when at logic zero.
goinputCommand to initiate a cycle.
intervalinputThe interval in clocks between waypoints.
stepoutputThe difference between successive waypoints.
incroutput The accumulated increments.

Host-interface ports

clk_hiinputHost-interface clock.
ready_hioutput Indicates that the table is ready to receive a block of data.
strobe_hi inputStrobe signal marking start of a packet.
bufwri_hiinputData-valid signal.
pipe_hiinputData pipe to logic.

Parameters

dwidth16Width of the ramp-waypoint data (to be interpolated.
awidth11Width of the waypoint address counter.
iwidth16Width of the inter-waypoint clock counter.
swidth10Width of the word holding the ramp step between waypoints.
blksize512Something

Notes

Example instantiation in Verilog:

wire		[2*15-1:0]	rampout;
wire		[  19:0]	interval;
wire		[   1:0]	quadrant;	// rotates among the four quadrants
wire		[15-1:0]	hostdatapath;

RampInterp
    #(.dwidth(15), .awidth(20), .iwidth(10), .swidth(8), .blksize(512))
    InterpIncr_inst (
        .clk(clk), 
        .reset(reset),
        .en(enable),
        .fiducial(fid),
        .go(go), 
        .interval(interval),
        .quad(quadrant),
        .ramp(rampout),
        .busy(busy),
        .valid(waypointvalid),
        .done(done),
        				// host-interface ports for the waypoint table
        .clk_hi(hostclock),
        .ready_hi(readytoload),
        .strobe_hi(strobe),
        .bufwr_hi(hostwrite),
        .pipe_hi(hostdatapath)
    );

Four-ramp sequence