ShiftReg.v

This module implements a shift register of variable width and depth.

Ports

clk	input	The clock input.
reset	input	Reset input, which clears the shift register.
en	input	Enable; the state is frozen when not asserted.
in	output	The data to be latched.
out	output	The latched and shifted output. Multiple words within the shift register may be accessed using the `outport` parameter.

Parameters

width	1	Data bit width.
depth	1	The depth of the shift register.
invert	"no"	Whether to invert the output, "yes" or "no".
outport	1	Selects the width in words of the output port, and can can range from 1 to `depth` to access all of the delayed `outport` words when needed.

Notes

Trivially instantiates out = in when depth is zero.
The module Register is also available in the source file. This module is a shift register without the reset and en ports. These ports are assigned 0 and 1, respectively.

Example instantiation in Verilog:

Depth three shift register.

wire			clk, reset, en;
wire		[11:0]	in, out;
ShiftReg #(.width(12), .depth(3))  Delay3 (
    .clk(clk), 
    .reset(reset),
    .en(en)
    .in(in), 
    .out(out)
);

An instance array that latches multiple words at different times:

wire			clk, reset;
wire			load0, load1, load2, load3;
wire		[15:0]	din0, din1, din2, din3;
wire		[63:0]	dout;
ShiftReg #(.width(16)) Register4 [3:0] (
    .clk(clk),
    .reset(reset),
    .en({load0, load1, load2, load3}), 
    .in({din0, din1, din2, din3}),
    .out(dout)
);