Table.v

This module implements a two-port ram buffer configured for reading 512 32-bit words (the A port), and writing 1024 16-bit words (the B port). The A and B ports are independent. The ram buffer is realized by the Xilinx RAMB16_S18_S36 primitive. The 32-bit words are clocked out the A port separated by a programmable interval. It is intended as a ramp waypoint table, although that is not explicitly part of its structure.

Ports associated with the ram-block A port

clkinputThe clock input.
resetinputThe reset input.
eninputAn enable input. The state of the table is mostly frozen when at logic zero.
fiducialinputA fiducial used for aligning the output of the table with other data sources and sinks.
goinputCommand to initiate a ramp cycle. The table output is later aligned with the fiducial.
intervalinputThe interval in clocks between waypoints.
addraoutputPointer to the current element of the table (0 to 511).
outoutputTable output (two parallel words).
busyoutputWhen asserted, indicates the table is currently outputting its data.
validoutputIs asserted for one clock cycle indicating that a table element on out is valid.
done  output  Is asserted for one clock cycle indicating that the table has been output and the sequence is ended.

Ports associated with the ram-block B port (host port)

clk_hiinputHost-interface clock.
ready_hioutputAsserted by Table indicating that it is able to receive a block of data.
strobe_hiinputAsserted briefly by the host interface indicating that it is beginning to transmit a packet of data.
bufwr_hiinputAsserted by the host interface indicating that data are currently valid on pipe_hi.
pipe_hiinputThe data path from the host interface.

Parameters

dwidth16width of the ramp-waypoint data (to be interpolated)
awidth10width of the waypoint address counter
iwidth16width of the inter-waypoint clock counter
blksize512number of I/Q pairs in the table

Notes

Example instantiation in Verilog:

wire		[19:0]	interval;
wire		[ 8:0]	address;
wire		[31:0]	waypoints;	// two words wide
wire		[15:0]	datapath_hi;

Table
    #(.dwidth(16), .awidth(9), .iwidth(20), .blksize(512))
    table_inst (
        		// port A
        .clk(clk), 
        .reset(reset),
        .en(en),
        .go(go), 
        .interval(10000),
        .addra(address),
        .out(waypoints),
        .busy(busy), 
        .valid(valid), 
        .done(done),
			// port B (host interface)
        .clk_hi(ti_clk),
        .ready_hi{ready_hi),
        .strobe_hi(strobe_hi),
        .bufwr_hi{writeenable_hi),
        .pipe_hi{hostdatapath_hi)
    );