Table.v

This module implements a two-port ram buffer configured for reading 512 32-bit words (the A port), and writing 1024 16-bit words (the B port). The A and B ports are independent. The ram buffer is realized by the Xilinx RAMB16_S18_S36 primitive. The 32-bit words are clocked out the A port separated by a programmable interval. It is intended as a ramp waypoint table, although that is not explicitly part of its structure.

Ports associated with the ram-block A port

clk	input	The clock input.
reset	input	The reset input.
en	input	An enable input. The state of the table is mostly frozen when at logic zero.
fiducial	input	A fiducial used for aligning the output of the table with other data sources and sinks.
go	input	Command to initiate a ramp cycle. The table output is later aligned with the fiducial.
interval	input	The interval in clocks between waypoints.
addra	output	Pointer to the current element of the table (0 to 511).
out	output	Table output (two parallel words).
busy	output	When asserted, indicates the table is currently outputting its data.
valid	output	Is asserted for one clock cycle indicating that a table element on `out` is valid.
done	output	Is asserted for one clock cycle indicating that the table has been output and the sequence is ended.

Ports associated with the ram-block B port (host port)

clk_hi	input	Host-interface clock.
ready_hi	output	Asserted by Table indicating that it is able to receive a block of data.
strobe_hi	input	Asserted briefly by the host interface indicating that it is beginning to transmit a packet of data.
bufwr_hi	input	Asserted by the host interface indicating that data are currently valid on pipe_hi.
pipe_hi	input	The data path from the host interface.

Parameters

dwidth	16	width of the ramp-waypoint data (to be interpolated)
awidth	10	width of the waypoint address counter
iwidth	16	width of the inter-waypoint clock counter
blksize	512	number of I/Q pairs in the table

Notes

The parameter 'interval' specifies the interval in clock cycles between transitions between I/Q pairs. Elements of each pair are output sequentially, and the same pair is output for the duration of each interval.
Because this module uses the RAMB16 primitive, blksize can be at most 512.
The width 'iwidth' must be large enough to accommode the number of clock cycles between waypoints. For example, if the clock frequency is 40 MHz, the waypoint table has 512 pairs, and the ramp duration is 1 second, then iwidth must be at least 17 bits to count to about 80,000.
The width awidth must be large enough to accommodate the number of points in the waypoint table. For example, if there are 512 points, then awidth must be at least 9.
The host side of the ram block is controlled by the host. It is not influenced by the enable input, which is for the local side of the block.
Because the two ports of the RAMB16 primitive are largely intependent, a read of port A can be initiated only a few cycles after the start of a write to the B port by the host interface.

Example instantiation in Verilog:

wire		[19:0]	interval;
wire		[ 8:0]	address;
wire		[31:0]	waypoints;	// two words wide
wire		[15:0]	datapath_hi;

Table
    #(.dwidth(16), .awidth(9), .iwidth(20), .blksize(512))
    table_inst (
        		// port A
        .clk(clk), 
        .reset(reset),
        .en(en),
        .go(go), 
        .interval(10000),
        .addra(address),
        .out(waypoints),
        .busy(busy), 
        .valid(valid), 
        .done(done),
			// port B (host interface)
        .clk_hi(ti_clk),
        .ready_hi{ready_hi),
        .strobe_hi(strobe_hi),
        .bufwr_hi{writeenable_hi),
        .pipe_hi{hostdatapath_hi)
    );