.v

This module ...

Ports | Parameters | Notes | Example | Timing diagram

Ports

clk	input	The clock input.
reset	input	The reset input.
en	input	An enable input. The state of the module is frozen when at logic zero.
go	input	Command to initiate a cycle.

Parameters

wd	Width of the host-interface data path (default 16).

Notes

Example instantiation in Verilog:

Diagram

8/21/2014