Threshold.v

This module is a binary threshold detector, that is, if the argument is below a specified power of two, a true is returned. There are four options. The argument bit width, whether it is signed, whether successive samples are to be interpreted as I and Q components, and whether the output is registered may be specified.

Ports | Parameters | Notes | Example

Ports

clk	input	The clock input. It is unused if the instance is unregistered and the input is not interpreted as successive I and Q components.
in	input	The input. These are only the uppermost bits.
low	input	The logic output indicating a below-threshold condition.

Parameters

w	4	Bit width of the input.
registered	"yes"	Whether the output is registered. It can be "yes" for registered, or anything else for not registered.
IQ	"yes"	Indicates whether successive samples are interpreted as I and Q components. Can be "yes" for I and Q compoents, or anything else for not.
sign	"yes"	Whether the input is interpreted as signed. Can be "yes for signed, and anything else for not signed.

Notes

When unsigned, the low output is true when all the bits of the input are low. When signed, the low output is true when all the bits are low, or all the bits are high.
When not registered and IQ is set to "no", the low output reflects the current sample. When registered and IQ is set to "no", the low output reflects the previous sample. When not registered and IQ is set to "yes", the low output reflects the current and previous samples. When registered and IQ is set to "yes", the low output reflects the previous two samples.

Example instantiation:

wire		signed	[15:0]	data;
wire				low;
Threshold
    #(.w(4), .registered("no"), .IQ("yes"), .sign("yes"))
    lim1 (.clk(clk), .in(data[15:12]), .low(low));