TripStack.v

This module is an event recorder that records the source and time stamp of events as they occur. It takes as input a set of logic signals that when active each signals an event, binary enclodes the active input with highest priority, and records that code in a register file (fifo) along with an externally provided clock (time stamp) and sequence number. The fifo is later read out by external logic clocking the next port while reading the out port. Total width of the fifo is 32 bits, while the depth is selectible by a parameter.

Ports | Parameters | Notes | Example | Timing diagram

Ports

clk	input	The clock input.
reset	input	Reset input. The signal clears the sequence counter and a bit that is set during readout.
next	input	The signal exposes the next record of the fifo during readout.
t	input	An input recorded along with the encoded trigger and sequence number. This port is not in any way interpreted, but is presumably a counter that when recorded serves as a time stamp.
trigs	input	The trigger inputs that are encoded and recorded in the fifo.
out	output	The output of the fifo.
count	output	This is the count of events in the fifo. The fifo is full when this count equals `depth`. Its bit width is `cw`.
armed	output	When asserted, indicates that the module is armed, i.e., capable of capturing events. It is not armed when 1) full, and 2) being read out. It is rearmed by a reset.

Parameters

dw	24	The bit width of the time (`t`) port.
tw	4	The base-two log of the number of triggers in the vector `trigs`. The number of triggers should be a power of two.
cw	`tw+1`	The width of the sequence counter.
stackdepth	`2^cw-1`	The depth of the fifo. It should be less than 2^cw.
detectedge	"no"	Normally events are logged on every clock cycle that an input is high. But when `detectedge` is not "no", an event is recorded only when an input changes to high.

Notes

This module records trip events until the fifo is full and will record no more events until it is reset.
The output of the fifo is always available at the out port. The next signal advances the fifo, making available the next element of the fifo. So full readout of the fifo involves stackdepth reads separated by depth − 1 next pulses. A reset pulse following readout prepares the module for further recording of events.
If the fifo is read out when the fifo had not been filled since the last reset, then the first element(s) have non-zero sequence number. The first valid event since the last reset has zero sequence number. The events in the remainder of the fifo are all valid and have increasing sequence number. When full, the first and last sequence number are zero and depth, respectively.
The count output is not incremented when the last event fills the stack to capacity. Distinguishing count = stackdepth and count = stackdepth − 1 is through the armed output: when the stack is at capacity, where armed has been cleared.
The count output can be used to skip over stale events in the fifo instead of using the sequence-number field.

Example instantiation:

wire	[23:0]	counter;
wire		t3, t2, t1, t0;
wire	[31:0]	result;
TripStack #(.dw(24), .tw(3), .cw(5)) ts (
	.clk(clk),	.reset(reset),			.next(next),
	.t(counter),	.trigs({t3, t2, t1, t0}),	.out(result)
);

TripStack.v

Ports

Parameters

Notes

Example instantiation:

Timing diagram (click to enlarge/shrink)