dcm_sys.v

Digital clock manager

Instantiates a digital clock manager (DCM) primitive. See the Spartan 3 data sheet. The file sdram_if.v has this comment:


//------------------------------------------------------------------------
// DCM
//   This ensures that the internal FPGA fabric clock (CLK) is phase 
//   aligned with the provided PLL clock (PLL_CLK) that is shared with 
//   the SDRAM at the board level.
//
//   The DCM here uses a phase delay to best align the fabric clock with
//   the SDRAM clock for optimum performance.  The phase delay was 
//   determined experimentally by testing the maximum "no-error" frequency
//   of RAMTester for various phase delays.
//------------------------------------------------------------------------

Ports

CLK_INinputThe clock input.
RST_INinputThe reset input.
CLK0_OUToutputThe buffered and deskewed clock output.
LOCKED_OUToutputStatus of the DCM's DLL lock.
CLKIN_BUFG_OUT  output  Input clock buffered.

File header

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.2.03i
//  \   \         Application : xaw2verilog
//  /   /         Filename : dcm1.v
// /___/   /\     Timestamp : 03/06/2007 22:44:51
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: xaw2verilog dcm1.xaw -st
//Design Name: dcm1
//Device: xc3s1200e-4ft256
//
// Module dcm1
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST

Diagram

Digital clock manager