mpx.v

This module implements a power of two-to-one multiplexor of variable bit width. The inputs are all concatenated into a single input vector. It is implemented as a binary tree in combinational logic.

Ports

sel	input	The multi-bit selector.
in	input	The data channels concatenated to a single vector, e.g., `{in3, in2, in1, in0}`.
out	output	The single-word output.

Parameters

wid	16	Data bit width of individual input channels and the output.
lev	2	The number of bits in the data selector. There should be 2^lev inputs in `in`.
invert	"no"	If "yes" the output is inverted; otherwise not.

Notes

Recursively instantiates itself.
Trivially instantiates out = in; when lev is zero.
When not all channels are used, all bits of the input in must still be filled or an error will result.

Example instantiation in Verilog:

// three-bit selector
wire	[11:0]	in0, in1, in2, in3, in4, in5, in6, in7, out;
wire	[2:0]	sel = 2'b010;
mpx #(.wid(12), .lev(3))  multiplexor (
    .sel(sel), 
    .in({in7, in6, in5, in4, in3, in2, in1, in0}), 
    .out(out)
);