This module talks to a Dallas (Maxim) chip DS1825 serial number/temperature chip over a one-wire interface. The code apparently comes from a Xilinx reference design for the Dallas chip DS2401 (see an app note from Xilinx). By inspection of the data sheets for the DS2401 and DS1825, the commands of the DS1825 appear to be a superset of the DS2401 set, apparently backward compatible. But the DS2401 does not have a thermometer, and the reference design does not support temperature conversions and retrieval from other chips.
------------------------------------------------------------------------------- -- Title : An interface to use 1-Wire Master -- Project : ------------------------------------------------------------------------------- -- File : onewire_iface.v -- Author : Rick Ballantyne rickb@Xilinx.com> -- Company : Xilinx, Inc. -- Created : 2001/03/15 -- Last Update: 2001/03/15 -- Copyright : (c) Xilinx Inc, 2001 ------------------------------------------------------------------------------- -- Uses : onewire_master.v, clk_div.v, defines.v ------------------------------------------------------------------------------- -- Used by : Any user system connecting to a 1-Wire device ------------------------------------------------------------------------------- -- Description: An interface to show how to use the 1-Wire Master -- -- It will output the data from the DS2401 byte by byte -- while data_valid is asserted. Totally 8 bytes of data will -- show up on the data bus in sequence of: -- Family code (x01 for DS2401) : 1 byte -- Serial number (e.g. xABCDEF) : 6 bytes -- CRC value (based on polynomial=X^8 + X^5 + X^4 + 1) : 1 byte -- So, user will get total 8 strobes of data_valid after the reset. -- -- It connects to the DS2401 through only one wire (sndq), -- which is a bidirectional data path with internal pullup -- resistor (about 13K Ohm, which is higher than the specification -- of 5K Ohm on the DS2401 datasheet). -- -- It uses a clock divider to generate a slow clock (1MHz) for -- the 1-Wire Master module from the system clock. Use a generic -- (CLK_DIV) to specify the divider ratio for different input -- clock rate. -- -- It generates a crc_ok signal which indicates all the data have -- been received/output and crc checking is OK if the parameter -- CheckCRC is defined. -- ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2001/03/15 1.0 Ballantyne Conversion from VHDL -------------------------------------------------------------------------------