xem_if.v

This module is an interface between logic and the Opal Kelly FrontPanel HDL library. It provides connections to the Opal Kelly wire ins and outs, trigger ins and outs, pipe ins and outs of both the throttled and unthrottle kind. There is also a multiplexor to loop back wire ins. All 512 wire-in bits, all 512 wire-out bits, two pipe ins, and two pipe outs are instantiated by this module.

Ports | Parameters | Notes

Host connections

hi_ininputHost-interface inputs.
hi_outinput    Host-interface outputs.
hi_inoutinputBidirectional host-interface signals.

User ports

ti_clkoutput    Host-interface clock used by logic.
wioutput512-bit wire in.
woinput512-bit wire out.
ep40trigoutput16-bit trigger in.
ep41trigoutput16-bit trigger in.
ep60triginput16-bit trigger out.
btpipeI_writeoutputTells logic that data are available in btpipeI_data.
btpipeI_dataoutputPipe-in data port associated with btpipeI_write.
btpipeI_write_83    outputThrottled pipe-in write signal.
btpipeI_block_83outputThrottled pipe-in strobe.
btpipeI_data_83inputThrottled pipe-in data.
ep83_rdyinputUsed by logic to tell the interface that logic is ready to receive data on btpipeI_data_83.
btpipeO_readoutputTells logic that the interface is reading data from btpipeO_data.
btpipeO_datainputThe pipe-out data port associated with btpipeO_read.
epB1_readoutputTells logic that the interface is reading data from epB_din.
epB1_dininputThe pipe data port associated with epB1_read.
readbacksinputA 512-bit expansion of the wire-in readback.

Parameters

wdWidth of the host-interface data path (default 16).

Notes