This module is an interface between logic and the Opal Kelly FrontPanel HDL library. It provides connections to the Opal Kelly wire ins and outs, trigger ins and outs, pipe ins and outs of both the throttled and unthrottle kind. There is also a multiplexor to loop back wire ins. All 512 wire-in bits, all 512 wire-out bits, two pipe ins, and two pipe outs are instantiated by this module.
ti_clk | output | Host-interface clock used by logic. |
wi | output | 512-bit wire in. |
wo | input | 512-bit wire out. |
ep40trig | output | 16-bit trigger in. |
ep41trig | output | 16-bit trigger in. |
ep60trig | input | 16-bit trigger out. |
btpipeI_write | output | Tells logic that data are available in btpipeI_data. |
btpipeI_data | output | Pipe-in data port associated with btpipeI_write. |
btpipeI_write_83 | output | Throttled pipe-in write signal. |
btpipeI_block_83 | output | Throttled pipe-in strobe. |
btpipeI_data_83 | input | Throttled pipe-in data. |
ep83_rdy | input | Used by logic to tell the interface that logic is ready to receive data on btpipeI_data_83. |
btpipeO_read | output | Tells logic that the interface is reading data from btpipeO_data. |
btpipeO_data | input | The pipe-out data port associated with btpipeO_read. |
epB1_read | output | Tells logic that the interface is reading data from epB_din. |
epB1_din | input | The pipe data port associated with epB1_read. |
readbacks | input | A 512-bit expansion of the wire-in readback. |