DDR_IQ.v

This module splits a double data rate data stream via the IFDDRRSE primitive, and applies offset-binary conversion and I/Q detection (1 - z^-2 filtering) of each stream (IQDtector.v).

Ports | Parameters | Notes | Example | Diagram

Ports

clk	input	The clock input.
reset	input	The reset input.
din	input	The double data rate data stream.
dout0	output	The first detected data stream.
dout1	output	The second detected data stream.

Parameters

wid

Width of the input data stream.

Notes

The outputs are one bit wider than the input due to the 1 - z^-2 filter.

Example instantiation in Verilog:

wire	[11:0]	in;
wire	[12:0]	d1, d2;
DDR_IQ #(.wid(12)) di (.clk(clk), .reset(reset), .din(in), .dout0(d1), .dout1(d2))