Divide.v

This module implements unsigned integer division returning a quotient and remainder. The quotient is optionally rounded.

Ports

clk	input	The clock input.
reset	input	The reset input restores the idle state.
go	input	A vector of triggers (see Trigger.v).
en	input	Enable; the state is frozen when not asserted.
dividend	input	Number to be divided.
divisor	input	Doing the dividing.
quotient	output	Quotient.
remainder	output	Remainder.
round	output	The remainder is greater than half the divisor.
busy	output	Division is in progress.
done	output	Done; asserted when the division is completed and data are valid.
error	output	Error; asserted in lieu of `done` if there was an overflow or the quotient is zero.

Parameters

width1	16	The bit width of the dividend.
width2	16	The bit width of the divisor.
width3	16	The bit width of the quotient and remainder.
rounding	"no"	Whether to round the quotient ("yes" or "no").

Notes

The width of the remainder is width2, the width of the divisor.
The done signal is asserted 1+width3 clock cycles after the go pulse.
The width of the quotient must be anticipated large enough to accommodate the maximum value encountered.
Dividend, divisor, quotient, and remainder are unsigned.
To get bits to the right of the binary point, add zeros on the right of dividend.
The reset input preempts the go and enable inputs; the go input preempts the enable input.
The outputs quotient, remainder, and round are held after the done pulse.

Example instantiation in Verilog:

wire		[21:0]	dividend;
wire		[ 7:0]	divisor;
wire		[ 9:0]	q;
wire		[ 9:0]	r;

Divide
    #(.width1(22), .width2(8), .width3(10))
    timer_inst (
        .clk(clk), 
        .reset(1'b0), 
        .go(go),
        .en(1'b1),
        .dividend(dividend),	// width1
        .divisor(divisor),	// width2
        .quotient(q),		// width3
        .remainder(r),		// width3
        .round(round),		// one bit
        .done(d),		// when quotient, remainder, and round are valid
        .error(e)		// no done when asserted
    );