Limiter.v

This module limits the magnitude of an I/Q data channel while preserving its phase. It takes as input a signed I, Q, -I, -Q sequence signal and outputs a signal whose magnitude is at most a given value (specified at compile time) while preserving its phase. It uses a serial Cordic rotator, so there is lag of about 1/3 μs.

Ports | Parameters | Notes | Example | Plots

Ports

clkinputThe clock input.
resetinputThe reset input.
eninputThe enable input.
goinputInitiates operation of the limiter. The limiter retriggers itself after it is started.
quadinputTwo-bit quadrant counter.
ininputThe input data stream. Its width is given by the width parameter.
outoutputThe output data stream. Its width is given by the width parameter.
busyoutput   Indicates that a rotation is in progress.
doneoutput 
activeoutputIndicates that the limiter is actively limiting the output.
diag1outputA floating diagnostic output.
diag2outputA floating diagnostic output.

Parameters

width16Bit width (default 16) of the data input and output.
steps11The number of clock cycles through which the Cordic rotation runs. It must be -1 modulo 4 at this point (7, 11, 15, ...), but it need not be greater than the number of data bits.
mag11319The magnitude at which the I/Q data are limited. It must be in the range of the data.
msbs4Because the Cordic converter becomes unstable for small input signal intensities, it is disabled when the input intensity is below a threshold given by 2-msbs smaller than full scale.

Notes

Example instantiation:

localparam w = 16;
wire			[w-1:0]	in, out;
Limiter
    #(.width(w), .mag(10720), .steps(w-5), .msbs(4))
    lim1 (
        .clk(clk),
        .reset(reset),		.en(1'b1),
        .go(startpulse),	.quad(quad),
        .in(in),		.out(out),
        .busy(busy),		.done(done)
    );

Plots (click to shrink/enlarge)

Plots of simulations.
Simulation

Simulation

I/Q plots of limiter input and output run on the controller board. There is sinusoidal modulation applied.
Simulation