Saturation.v

This module implements combinational arithmetic saturation of a signed word. It has two modes: the first saturates to a bit width less that the input width; the second saturates to a maximum magnitude. The parameter mag determines which mode is instantiated: the first when zero, the second when nonzero.

Ports

clk	input	The clock input used with the `registered="yes"` option.
in	input	The input.
out	output	The output.

Parameters

wIn	16	The bit width of the input port `in`.
wOut	15	The bit width of the output port `out`.
wid	wIn	The bit width of the input. A synonym of `wIn`.
sat	wIn-wOut+1	In the first mode, the number of bits of saturation. In this mode, the output has `sat-1` bits less width than the input. It should be zero when the module is used in the second mode, where `mag` is nonzero. When the default is overridden, `sat`'s value as per these rules take precedence over `wOut`.
mag	0	In the second mode, the value at which to saturate the output. The first mode is selected by `mag = 0` and `sat = 0` .
registered	"no"	To register the output, use `"yes"`. A clock input must be provided.

Notes

An error is flagged when both mag and sat are nonzero.
The module is implemented with a two-level multiplexor (mpx.v).

Example instantiation in Verilog:

wire	[14:0]	sig;
wire	[11:0]	sig_sat;
Saturation #(.wid(15), .sat(4)) sat_inst (.in(sig), .out(sig_sat));

wire	[12:0]	sig;
wire	[12:0]	sig_sat;
Saturation
    #(.wid(13), .sat(0), .mag(1187))
    sat_inst (.in(sig), .out(sig_sat));