ScopeTraces.v

This module manages a set of eight dual-port 1-kword ram blocks for capturing waveforms and readout by the host computer. Their trigger logic, when triggered, manage the recording of the signals at rates that depend on the current zoom. An interface to a data pipe allows the data to be read out on demand.

Eight signals are saved in the memories at an interval determined by the zoom setting. All signals are recorded simultaneously. Busy and done signals indicate the module is recording and marking the end of recording, respectively.

The readout of the memories by a host through the host side of the ram blocks is initiated by a pulse on the go_hi port. Data are gated onto the output port on the clock cycle following each clock cycle that the read signal is asserted. Timing is as described on pages 37 and 38 of the FrontPanel manual (2005-2007). Busy and done signals are also available for monitoring that side of the ram blocks.

Start of acquisition is always aligned with a zero-quadrant fiducial. Because there are delays built into the various data paths of the controller logic, zero quadrants of most signals in the controller are not be aligned with scope acquisition, but are instead shifted by one or more clock cycles. Thus, to record signals with quadrants aligned with the scope, delays must be applied to the signals on a case-by-case basis prior to application to a scope channel. These delays must be applied by shift registers within the code.

Signal-side ports

clk	input	Data-side clock.
reset	input	Reset input
go	input	Two-bit trigger (Trigger.v).
interval	input	The interval between recorded words (currently 1 to 4096).
din	input	Input data as an 8*16-bit vector of eight concatenated signals. The last (least significant) is output first.
busy	output	Indicates that recording data is underway.
done	output	Indicates that recording data is done.

Host-interface-side ports

clk_hi	input	The host-interface clock.
go_hi	input	Initiates the sequencer for a readout. It can be any time before `read_hi` is first asserted.
read_hi	input	Data on `dout_hi` are valid on the clock cycle following each clock cycle that `read_hi` is asserted. `read_hi` should be asserted a total of 8*1024 clock cycles for full readout of the memories in sequence, although they need not be sequential clock cycles.
busy_hi	output	Indicates a readout is in progress.
done_hi	output	Asserted for one clock cycle indicating a readout has finished.
dout_hi	output	Data out in sequence, which is valid the clock cycle after each cycle `read_hi` is asserted.
sample_hi	output	Is asserted when a sample is taken – a sample pulse.

Parameters

dw	16	Data bit width.
aw	13	An internal counter width, which is fixed at 13 by the `RAMB16` primitive and the number of inputs, and should not be changed.
gb	1	The number of trigger bits applied to the `go` port.

Notes

The dual-port memories are implemented as RAMB16_S18_S18 primitives (see the Xilinx Spartan-3 manual).
Readout should not be at the same time as recording because loss of data may occur.

Example instantiation in Verilog:

wire		clk, reset, arm, go, busy, done;
wire	[15:0]	sig0, sig1, sig2, sig3, sig4, sig5, sig6, sig7;
wire		trigger_hi, read_hi, busy_hi, done_hi;
wire	[15:0]	pipe_hi;
ScopeTraces
   #(.dw(16), .aw(13), .gb(2)) 
   Scope (
	// signal side
      .clk(clk),
      .reset(reset),
      .go({arm, go}),			// two-stage trigger
      .interval(13'b5),			// currently fixed at 13 bits
      .din({sig7, sig6, sig5, sig4, sig3, sig2, sig1, sig0}),
      .busy(busy),
      .done(done),			// one-clock pulse
	// host-interface side
      .clk_hi(clk_hi),
      .go_hi(trigger_hi),
      .read_hi(read_hi),
      .busy_hi(busy_hi),
      .done_hi(done_hi),		// one-clock pulse
      .dout_hi(pipe_hi)
   );