SerialRx.v

This module implements an asynchronous serial receiver with variable data rate, variable number of data bits, variable stop bits, and optional parity. It is compatible with SerialTx.v.

Ports

clk	input	The clock input.
sin	input	The serial data stream.
out	output	Data word out in parallel.
valid	output	When asserted, indicates that data are valid on the out port.
error	output	Indicates a parity error occurred.

Parameters

dwidth	8	The number of data bits in the serial frame.
parity	"n"	Parity: "n", "e", and "o" for none, even and odd, respectively.
stop	1	The number of stop bits.
factor	44	The number of clock cycles per serial period.
sampledelay	66	The number of clocks after the detected edge of the start bit to the start of data sampling.

Notes

The serial frame consists of a logic-one start bit, the data bits, an optional parity bit, and one or more logic-zero stop bits.
The parameter is nominally 1.5 times factor. Perhaps another value is optimal.

Example instantiation in Verilog:

wire		[11:0]	data;

SerialRx
    #(.dwidth(12), .parity("e"), .stop(2), .sampledelay(66), .factor(44))
    recv_inst (
        .clk(clk), 
        .sin(serialdata),
        .out(data)
        .valid(valid),		// received a serial frame
        .error(e)
    );