SerialTx.v

This module transmits a serial frame of data. The serial frame consists of a start bit followed by the data bits msb first, an optional parity bit, and one or more stop bits. The number of data bits, parity, and the number of stop bits may be specified. The done signal indicates the data are all clocked out and a new transfer may be started. Data are latched with the first rising clock edge simultaneous with the go pulse. This module is compatible with SerialRx.v.

Ports

clk	input	The clock input.
go	input	Input data are sampled on the next rising edge of clock and the transfer initiated.
in	input	The paralle data to be transmitted.
sout	output	The serial stream output by this module.
done	output	When asserted, indicates that the data are transmitted and a new word may be transmitted.

Parameters

dwidth	9	The number of data bits in the serial frame.
parity	"n"	Parity: "n", "e", and "o" for none, even and odd, respectively.
stop	1	The number of stop bits.
factor	16	The number of clock cycles per serial period.
ctrwidth	7	The bit width of an internal counter. Must be large enough to count to `dwidth` plus parity plus stop plus one.

Notes

The go flag initiating a new transfer can be simultaneous with the done flag signaling completion of the previous transfer.
The parameter sampledelay is nominally 1.5 times factor. Perhaps another value is optimal.

Example instantiation in Verilog:

wire		[11:0]	data;

SerialTx
    #(.dwidth(12), .parity("e"), .stop(2), .factor(44), .sampledelay(66))
    recv_inst (.clk(clk), .go(go), .in(data), .sout(s), .done(e));