Timer.v

On a go trigger pulse, a done pulse is output a programmed interval later. The internal interval counter and a busy signal are available, and the counter may count either up or down. A multi-level trigger may be input (Trigger.v).

Ports

clk	input	The clock input.
interval	input	The timed interval.
reset	input	Reset input, which restores the idle state to both the timer itself, and its trigger logic (Trigger.v).
go	input	A vector of triggers.
en	input	Enable; the state is frozen when not asserted.
busy	output	Timer is running; not asserted while awaiting triggers.
trigstate	output	The state of the trigger.
done	output	Done; asserted when the interval is counted.
ctr	output	The counter, which counts on each enabled clock cycle.

Parameters

width	32	The bit width of the internal counter; must be large enough to hold `interval`-1. The width of `interval` is one greater.
gobits	1	The number of triggers; see Trigger.v.
direction	"up"	The direction `ctr` counts, either "up" or "down".

Notes

The parameter width limits the maximum interval that can be counted. Choose a value that can accommodate the largest value anticipated for the application. For an interval = 2ⁿ, width must be ≥ n. The width of interval is one greater than width, so that it can hold the number 2^width.
At the completion of the time, which is when the done port is asserted, the final value of the counter ctr is held: interval-1 for direction = "up" and 0 for "down".
A reset resets the state of the timer, regardless of its state.
The go signal reinitializes the timer for a new cycle regardless of the timer's state, although reset has precedence.
Multiple go bits implement a multi-level trigger as per Trigger.v. The parameter gobits = count in the latter module. gobits = 1 (default) implements a simple trigger.
The timer holds its state when en is deasserted, although reset and go have precedence.
The interval is latched when if it is nonzero and when the counter is triggered, i.e., the trigger sequence completes. Similarly, busy becomes active when the trigger sequence completes.
If interval is zero, the done output echos the output of the trigger sequencer, whether it be single or multi-level.
All operations are synchronous with the rising edge of the clock.

Example instantiation:

wire                    tr[1:0];
wire			ctr[11:0];
Timer
    #(.width(12))
    timer_inst (
        .clk(clk), 
        .interval(38),		// need not be a constant, nor constant
        .reset(1'b0), 
        .go({arm, go}), 	// can have one or more triggers (see Trigger.v)
        .en(1'b1),		// need not be constant
        .trigstate(tr),
        .done(done),
        .ctr(ctr)
    );