Builds for different rf systems

Compilation flow

The code for the controller logic has been written so that different rf systems can be flexibly targeted by the compilation of the code. This done through `ifdef .. `else .. `endif and `define compiler directives specifying what options are and are not to be compiled into the build. In code, this level of conditional compilation is reminiscent of block-oriented structured programming of the 1970s, and is amenable to documentation by flow chart. The long figure on the right should be viewed in this context, i.e., as a chart of compiler flow and not of program or signal flow. Thus the source code for the controller logic is by design the same for all the systems, with the exception of the Verilog `defines specifying the target and options. Even board versions with their different external connections are coded, although code for older boards quickly becomes obsolete.

There are several rf systems in NSLS-II targeted by builds of the logic, namely,

They differ substantially in their functions. For example, some of the systems use feedback, while others do not; the storage ring has a soft trip module for controlled ramp downs in response to some trips, while others do not; some systems are even unpowered; and differing interlock needs are accommodated, etc.

When logic is instantiated, it is tied into sources and destinations such as the host interface; when not instantiated, those sources and destinations are available for other uses. These connections are made in the appropriate `if ... `else ... `endif blocks.

Configuration `defines

Below is a list of the symbols that may be defined, and how they affect the build.

There are defines for different controller-board revisions, although the use of the defines has not be developed.

Controller board revisions also require revised pin assignments in the llrf_xem.ucf file that is part of the build.

There are also Verilog `defines for specific targets.

A readback word is allocated to return the states of some of these parameters. See LogicConfiguration.xls for more details. This word is incorporated into the board serial number returned by BoardSerialNumber() implemented in rfboard.m.

The build code

The configuration of the build is available to the host at run time via a 32-bit field of the wire-out readouts. Exact bit assignments are in the configuration spread sheet.

Source code segment configured for the storage ring CESR cavities (1/2012)

/************************** build options ******************************/
// platforms
	`define StorageRing
// 	`define Booster
//	`define Linac
//	`define HHC
//	`define SPB
//	`define PBU
//	`define MO
	
`ifdef MO                           			// for Master Oscillator version
	 `define Linac
	 `define ofl_value 20
`else
	 `define ofl_value 0
`endif

`ifdef HHC
	`define	Superconducting				// for superconducting cavity
`else
	`define	PoweredSystem				// powered systems
	`ifndef	Linac
		`define	Feedback			// systems with feedback 
		`ifdef	StorageRing
		 `define	SoftTrip		// soft-trip logic (RampDown.v)
		 `define	ReferenceProcessor	// reference processor
		 `define	Superconducting		// for superconducting cavity
//		 `define	ffRampInterval		// diagnostic mode; comment for ff zoom control
		`endif
		`ifdef Superconducting
		  `define sibits 5			// fb_loop bit parameter: SC
		`else
		  `define sibits 7			// fb_loop bit parameter: NC
		`endif
	`endif
`endif

	`define	InternalFiducial			// bunch fiducial, from AVAGO1 or synthetic
//	`define	TemporaryReference			// temporary internal reference
	`define	Quench					// SC quench detection
//	`define	Vacuum					// vacuum interlock and/or conditioning
	`define	TuningControl				// tuning phase error and control
	`define	PPS					// another interlock module
	`define	LOAboveRF				// LO frequency is greater than RF frequency
	`define	LimitLevel 5276				// limiter level
	`define	BunchRevInterval 528			// clocks between bunch revolution fiducial
//	`define	ChannelTest				// for testing of the ADC channels
	`define	OpalKelly				// Opal Kelly vs ethernet
/***********************************************************************/