owRead (OneWire.v)

This module implements one or more 1-wire bus-master read cycles. The 1-wire bus is a single-wire bi-directional bus standard originally authored by Dallas Semiconductor. It has a master/slave architecure, capable of handling multiple slave devices. This module reads a configurable number of bits from the bus, with the slot timing intervals in clocks settable via parameters. The defaults apply to a 1-MHz clock.

Ports | Parameters | Notes | Example | Timing diagram

Ports

clk	input	The clock input.
reset	input	The reset input.
go	input	Pulse to initiate a cycle.
data	output	The word read from the bus. Data remain valid until the instance is restarted.
dq	in/out	The 1-wire bus. When undriven, it goes high.
busy	output	Indicates that the instance is busy outputting a word.
done	output	Asserted for a clock when the instance has completed its operation.

Parameters

w	Width of the bit counter (default 3).
b	The bit count of the word read from the bus (default 8). Must be at most `2^w`.
w1	Bit width of the timer for the read-slot pulse duration (default 2).
t1	Duration in clocks of the pulse signaling the read cycle to the device (default 4). Must be at most `2^w1`.
w2	Bit width of the timer marking when to sample the bus (default 4).
t2	When to read the bit from the 1-wire bus, measured in clocks from the start of the read slot (default 14). Must be at most `2^w2`.
w3	Bit width of the timer for the read-slot duration (default 6).
t3	Duration of the read slot in clocks (default 64). Must be at most `2^w2`.

Notes

The done output is pulsed after all the read slots have elapsed, and not just after the last bit has been sampled.
The defaults apply to a 1-MHz clock.
See also: 1-wire overview, the DS1825 chip, the owWrite module, the owRead module, and the owResetPresence module.

Example instantiation in Verilog:

Read the device ROM code.

// read 64-bit ds1825 rom data
tri1			onewire;
wire			busy, done, go;
wire		[63:0]	romdata;
owRead
    #(.w(6), .b(64))
    readrom (
        .clk(clk),		.reset(reset),
        .go(go),		.dq(onewire),
        .data(romdata),
        .busy(busy),		.done(done)
    );

This instance reads the bus until it receives a logical 1. If no device is present or responds, then it exits after the first cycle.

// wait for a device operation to finish
// device is returning zeros as long as the operation is running
// then returns 1 (e.g., DS1825 temperature conversion)
tri1		onewire;
wire		clk, reset, go, busy, donea, done, flag;
owRead
    #(.w(1), .b(1))
    waitfordone (
        .clk(clk),		.reset(reset),
        .go(go || donea && !flag),
        .dq(onewire),		.data(flag),
        .busy(busy),		.done(donea)
    );
wire		done = donea && doneflag;

2/4/2015