owWrite (OneWire.v)

This module implements 1-wire bus-master write cycles. The 1-wire bus is a single-wire bi-directional bus standard originally authored by Dallas Semiconductor. It has a master/slave architecure, capable of handling multiple slave devices. This module clocks a bit vector onto the bus, with the write-slot timing intervals in clocks settable via parameters. The defaults apply to a 1-MHz clock.

Ports | Parameters | Notes | Example | Timing diagram

Ports

clk	input	The clock input.
reset	input	The reset input.
go	input	Command to initiate a cycle.
data	input	The word to be written to the bus.
dq	in/out	The 1-wire bus. When undriven, it goes high.
busy	output	Indicates that the instance is busy outputting a word.
done	output	Asserted for a clock when the instance has completed its operation.

Parameters

w	Width of the bit counter (default 3).
b	The bit count of the word to be written to the bus (default 8). Must be at most `2^w`.
w1	Bit width of the timer for the write-slot pulse duration.
t1a	Write-1 pulse duration in clocks (default 4).
t1b	Write-0 pulse duration in clocks (default 60).
w2	Bit width of the timer for the write-slot duration (default 6).
t2	Duration of the write slot in clocks (default 64). Must be at most `2^w2`.

Notes

The done output is pulsed after the write slots have elapsed, and not just after the bus has been pulsed by the last bit.
See also: 1-wire overview, the DS1825 chip, the owWrite module, the owRead module, and the owResetPresence module.

Example instantiation in Verilog:

// write ROM command to device
wire				clk, romgo, rombusy, romdone;
wire			[7:0]	romcmd = 8'h33;
tri1				onewire;
owWrite #(.w(3), .b(8)) SendROMCommand (
    .clk(clk),			.reset(reset),
    .go(romgo),			.data(romcmd),
    .dq(onewire),
    .busy(rombusy),		.done(romdone)
);

2/4/2015