NetworkAnalyzerPipelined (NetworkAnalyzer.v)

This module acts as a network analyzer: it generates a synthesized (DDS) sine wave for excitation of a system being measured, and Fourier analyzes one or more signals from the system for their response functions from the point of excitation. The Fourier analysis consists of computation of sine and cosine integrals over a specified number of clocks. A dead time allows transients to die away. To excite a system, the sine wave generated by the DDS is added to a signal passing in and out through a pair of ports. The intensity of the excitation may be selected as a power of two. The DDS is useful for all excitation frequencies within the sampling bandwidth. Up to 15 signal channels may be intantiated, the number set by a parameter specified at build time.

This module is a full-bandwidth network analyzer: it can measure at any frequency in the sampling bandwidth with resolution determined by the phase-accumulator bit-width parameter wpa.

f_res = f_s × 2^-wpa

For example, with f_s = 40 MHz and wpa = 22, the resolution is about 10 Hz. The module's use is significantly simpler than that of the modules with serial DDSs.

The DDS frequency is selected via numerical logic input vectors, as is the duration of integration. The sine and cosine integrals are accessible by the host through a throttled pipe. The up to 30 integrals are transferred as a block (illustrated below), each integral as a double word, along with a double word containing the integration time as a clock count, and a filler double word. The block size transferred is 32 double words (128 bytes) regardless of the number of channels instantiated.

I₁, Q₁
I₂, Q₂
...
I_nchans, Q_nchans
0, 0
...
0, integration time

The following figure shows the open-loop response of the system with the output connected to the cavity input and measured over the entire sampling bandwidth. Besides showing the response of the analog electronics of the controller, it also shows the z = ±1 nulls in the response of IQDetector. The dotted lines are at the IF2 frequency and its negative.

The delay value in the phase plot is slightly low due to a phase-unwrapping glitch at the frequency midpoint (z = -1) where there is a zero in the response.

Ports

clk	input	The clock input.
reset	input	The reset input, used return the network analyzer to the idle state, including stopping DDS output.
go	input	Arm/trigger vector that initiates an analysis sequence. A single bit simply triggers the start.
gonow	output	Is asserted for a clock when the final trigger condition is met. This is the pulse that finally initiates an analysis sequence.
quad	input	The I/Q quadrant fiducial.
freq	input	The frequency in terms of the phase increment on the `2^wpa` scale of the DDS phase accumulator, which is incremented every clock.
acquirecount	input	Integration time in clocks.
ddsI0, ddsQ0	output	The I and Q outputs of the DDS. These signals are the provided to the fourier analyzers' reference inputs.
ddsI, ddsQ	output	The `ddsI0` and `ddsQ0` outputs scaled by `2^intensity-15`.
signals	input	The signals in I/Q data streams to be analyzed. There are `nchans` of them concatenated into a single vector.
fourier	output	The output Fourier cosine and sine integrals. There are `2*nchan` of them concatenated into a single vector.
busy	output	Indicates that a measurement sequence is in progress, including the leading dead time.
valid	output	Asserted for one clock cycle to indicate that an analysis sequence has completed and data are available at `fourier` for readout.
intensity	output	The intensity of the DDS output. The DDS output is scaled downward by powers of two selected by `intensity`: `dds = 2^intensity-15` × full scale.
srcin	input	A system I/Q data stream to which is added the dds excitation.
srcout	output	The `srcin` port with the scaled dds excitation added.
hi_clk	input	Host clock of the host interface.
hi_strobe	input	Indicates that the host is initating a read sequence.
hi_ready	output	Indicates that the logic is ready to provide data to the host.
hi_read	input	Asserted by the host when reading data from the data port.
hi_data	output	Provides data to the host.

Parameters

Parameters, their defaults, and descriptions:

nchans	1	The number of fourier channels instantiated. It is the number of signals concatenated into the `signals` vector to be analyzed.
wd	16	The bit width of the signals to be analyzed.
wdds	12	The bit width of the DDS output ports `ddsI,Q` and `ddsI0,Q0`.
wo	24	The bit widths of the Fourier integrals in ports `fourier` and `meas`.
wpa	wdds+1	The bit width of the `freq` port and the phase accumulator internal to the dds. It controls the frequency resolution (see the note below). The `freq` port is added to the phase accumulator every clock.
wtc	10	The bit width of the `acquiretime` port and integration-time counter.
ofl	wtc	The number of integrator overflow bits. Integration times must always be short enough that the integrator does not overflow during the analysis cycle.
fapb	12	The number of accumulator precision bits. These least-significant bits are used during accumulation but discarded from the output as a means to control accumulated quantization noise. The value `ofl/2` is often a good choice.
ws	14	The bit widths of the source input and output ports `srcin` and `srcout`.
wi	4	The `intensity`-port bit width. It need not be greater than `ceiling(log₂(wdds))`.
whi	16	The host-interface bus width.

Notes

The DDS module employs a pipelined Cordic module that generates the output I/Q vector every clock. Because of this, any frequency in the sampling bandwidth may be generated. This allows analysis at arbitrary offsets from the carrier, including at other revolution lines where coupled-bunch responses can be measured.
To analyze approximately at frequency f, set
```
freq = round(f × 2^wpa/ f_s)
```
where f_s is the system sample rate. The exact frequency at which analysis runs isf = f_s × freq/2^wpa

The duration of integration is best set to a multiple of the modulation period, i.e., a multiple of 2^wpa/freq. The exact multiple chosen is a balance between greater accuracy with long integrations, the convenience of quicker measurements, and total clocks less than 2^wtc. Another consideration is avoiding overflow, which depends on ofl and the excitation intensity through intensity. There is dead time inserted before integration actually starts and after the DDS is started that allows the system under test to stabilize under the excitation. Its duration is fixed at half the integration time. Saturation is applied to the output at srcout so that it cannot wrap. The data on port fourier persist after an analysis sequence. In terms of slices of the XC3S1500 device, with wdds = 12, wd = 16, and ws = 14, the network analyzer requires about 7.4% plus about 1% per channel. See the figure to the right. See also DDSPipelined, FourierIQ, and SignedMultiplyAccumulate. The host-interface ports are compatible with the Opal Kelly FrontPanel block-throttled pipe timing.

Example instantiation: localparam chans = 3, // number of channels wd = 15, // signals to be analyzed ws = 14, // through ports wdds = 12, // dds width wo = 24, // fourier output wpa = 19, // phase accumulator wtc = 11, // turn counter ofl = 20, // overflow whi = 16; // host interface // network analyzer setup parameters wire [wtc-1:0] integrationtime; wire signed [wpi-1:0] frequency; wire [wi-1:0] intensity; // DDS outputs wire signed [wdds-1:0] I0, Q0; // unscaled wire signed [wdds-1:0] I, Q; // scaled // input signals to be analyzed wire [wd-1:0] sig1, sig2, sig3; // through ports into which dds is injected wire signed [ws-1:0] din, dout; // host interface ports wire hi_clk, hi_strobe, hi_ready, hi_read; wire [whi-1:0] hi_data; NetworkAnalyzer #(.nchans(chans), .wd(wd), .ws(ws), .whi(whi), .wdds(wdds), .wo(wo), .wpa(wpa), .wpi(wpi), .wtc(wtc), .ofl(ofl)) na ( .clk(clk), .reset(stoppulse), .go(startpulse), .gonow(nagonow), .quad(quadrantfiducial), .freq(frequency), .dampcount(dampingtime), .intensity(intensity), .acquirecount(integrationtime), .ddsI0(I0), .ddsQ0(Q0), // unscaled .ddsI(I), .ddsQ(Q), // scaled .signals({sig3, sig2, sig1}), .busy(naBusy), .ddstick(ddst), .turntick(nact), .valid(naValid), // ff data stream .srcin(din), .srcout(dout), // host interface .hi_clk(hi_clk), .hi_strobe(hi_strobe), .hi_ready(hi_ready), .hi_read(hi_read), .hi_data(hi_data) );