Verilog modules
- llrf_xem.v
- Top level logic.
- Accumulator.v
- Power-of-two averaging of a signed input stream.
- CavityTuning.v
- Cavity tuning logic.
- CoRotator.v
- Performs Cordic rotations of two vectors, one is rotated to zero (or 180-degree) angle, the other is rotated through the same angle either in the same direction, or the opposite direction. Very light weight in terms of real estate.
- dcm_sys.v
- A low-level module used in the SDRAM control logic to distribute a deskewed clock.
- Debounce.v
- Aligns pulses with a clock.
- DDR_IQ.v
- Double data rate separation and I/Q demodulation.
- DDS (DDS.v)
- Direct digital synthesizer, serial version.
- DDSPipelined (DDS.v)
- Direct digital synthesizer, pipelined version.
- Divide.v
- Integer divider.
- DoubleTimer.v
- A timer for sequences of pulses separated by programmaable intervals.
- fb_loop.v
- Part of the feedback-loop data path providing gain and phase shift.
- ffSetpointTable.v
- Provides a table for feed forward signals, and outputs the table to other logic at various rates.
- InterpIncr.v
- Interpolator primitive.
- IQDetector.v
- Separates double data rate streams from the ADCs and filters the with response function is 1 - z-2.
- jump5.v
- Merges the feed forward signal into the feedback data path.
- Limiter.v
- Limiter.
- mpx.v
- Power of two binary-tree multiplexor in combinational logic.
- NetworkAnalyser (NetworkAnalyzer.v)
- Network analyzer, serial DDS version.
- NetworkAnalyzerPipelined (NetworkAnalyzer.v)
- Network Analyzer, pipelined DDS version.
- OffsetBinary.v
- Offset-binary conversion in combinational logic.
- OneWire.v
- Talks to devices over the 1-wire bus. There are low-level modules for writing single bits, reading single bits,, testing for device presence, and a module for talking to the Maxim DS1825 chip.
- PhaseDifference.v
- Takes as inputs two I/Q data streams, and outputs the signal phases and magnitudes, and the phase difference. It is intended for use in the cavity-tuning subsystem.
- QuadrantLatch.v
- Register used to sample if signals during the first and second rf quadrants.
- PriorityEncoder.v
- A priority encoder.
- RampDown.v
- Quick ramp down for a soft trip.
- RampInterp.v
- Interpolated ramp for use in the booster rf system.
- ReferenceProc.v
- Shifts the phase of the feedback setpoint by the phase if the reference rf input.
- Register (ShiftReg.v)
- Simple synchronous register – no reset or enable.
- Rotator (Rotator.v)
- Rotates an I/Q vector through a given angle (serial version).
- RotatorPipelined (Rotator.v)
- Rotates an I/Q vector through a given angle (pipelined version).
- Saturation.v
- Saturation of signed data in combinational logic.
- ScopeTraces.v
- Multi-channel buffered data acquisition and host interface.
- SignalSampling.v
- Low-level module used in ffSetpointTable.v to synchronize sampling of rf signals returned through Opal Kelly end points to the feed-forward table output cycle.
- sdram_if.v
- An interface to the SDRAM control logic in sdramctrl.v. It implements the circular-buffer function.
- SerialRx.v
- Serial receiver parameterized for number of data and stop bits, and parity.
- SerialTx.v
- Serial transmitter parameterized for number of data and stop bits, and parity.
- ShiftReg.v
- A shifter register of variable width and depth.
- Table.v
- Dual-port RAM interfaced to an Opal Kelly pipe.
- Threshold.v
- Tests for a set of msbs being all zero or all one.
- Timer.v
- A versatile timer.
- Trigger.v
- A multi-stage trigger sequencer.
- UpConv.v
- Doubles the output data rate and removes unwanted lines prior to digital-to-analog conversion.
- xem_if.v
- Mediates data movement between logic and the host computer.